The present invention relates to a plasma display panel and a method of driving same. More particularly, the present invention relates to a technology to improve the display contrast while maintaining the performance stability in a plasma display panel of ALIS (Alternate Lighting of Surfaces) method in which every space between adjacent sustain electrodes is used as a display line.
A plasma display panel is a device in which a space of about 100 micron width between two glass substrates on which electrodes are formed is filled with mixed gases, consisting of gases such as Ne and Xe, for discharge, a voltage greater than the discharge start voltage is applied to cause a discharge to occur, and fluorescent materials formed on the substrates are activated, to emit light, by the ultraviolet rays generated by the discharge.
FIG. 1 is a diagram that shows the structure of a display apparatus employing a plasma display panel. In a display panel 10, first electrodes 1 and second electrodes 2 arranged in parallel are formed, and third electrodes 3 are formed so as to be perpendicular to them. The first and the second electrodes are used mainly to perform a sustain discharge for display light emission, and the first electrodes are referred to as X electrodes, and similarly the second electrodes, as Y electrodes, here. A sustain discharge is performed by applying a voltage pulse repeatedly between the X electrode and the Y electrode. Moreover, some electrodes serve as a scanning electrode when display data is written. (In this example, the Y electrode is the scanning electrode.) On the other hand, the third electrode is used to select a display cell that is made to emit light in each display line, and a voltage is applied to perform a write discharge to select a cell to be made to discharge between the first or the second electrode and the third electrode. The third electrode is referred to as an address electrode here. These electrodes are connected to drive circuits to generate a voltage pulse to meet each purpose. As shown schematically, the X electrodes are connected to an X electrode drive circuit 12 and common drive signals are applied to the X electrodes. The X electrode drive circuit 12 has an X sustain pulse circuit 13 and an X reset voltage generate circuit 14. The Y electrodes are connected to a Y electrode drive circuit 15. The Y electrode drive circuit 15 has a scanning driver 16, a Y sustain pulse circuit 17, and a Y reset/address voltage generate circuit 18. The address electrodes are connected to an address driver 11. Because a display apparatus employing the plasma display panel is described in detail in EP 0 762 373 A2, and so on, which will be described later, no description is provided here.
FIG. 2 is a diagram to describe in detail the display panel part of the apparatus shown in FIG. 1. The plural X electrodes 1 and the plural Y electrodes 2 are arranged in parallel. Display lines L1 through L4 are shown here. In addition, partitioning walls 5 are formed to separate the address electrodes 3 and the display cells. Therefore, each display cell is separated by the partitioning wall 5 in the direction that the X electrodes and the Y electrodes extend.
FIG. 3 is a diagram that shows the structure of a frame to illustrate the drive sequence of the apparatus shown in FIG. 1. Because the discharge of a plasma display panel has only two values, that is, ON or OFF, the degree of brightness, that is, the gradation scale is represented by number of light emissions. For more efficient performance, a frame is divided into plural subfields, for example, 10 subfields. Each subfield comprises a reset period, an address period, and a sustain discharge period (also referred to as sustain period). In the reset period, an action is carried out to set all the cells to a uniform state, for example, a state in which wall charges are eliminated, regardless of the state of the cell whether ON or OFF in the preceding subframe. In the address period, a selective discharge (address discharge) is carried out to determine whether the cell is ON or OFF according to the display data, and wall charges to set a cell into the ON state are formed. In the sustain discharge period, a discharge is carried out repeatedly on the cell in which the address discharge is performed to emit a specified light. The length of the sustain discharge period, that is, the number of light emissions, differs from subfield to subfield. For example, an arbitrary gradation scale display can be attained by specifying the ratio of numbers of light emissions in the subfields 1 through 10 to 1:2:4:8 . . . , and making each cell emit light after selecting subfields according to the brightness of the cell for display.
FIG. 4 is a diagram that shows the light emission state of the reset discharge to illustrate the display contrast. To raise the display contrast, it is advisable to suppress the discharge intensity of the display cells for black display as much as possible. Therefore, it is preferable to prevent the discharge that does not have relation to display from occurring. The address discharge, however, may not be made to occur even if the specified voltage is applied between electrodes, if there is not a certain amount of suitable ions or metastable atoms. Therefore, the reset discharge is carried out in all the cells periodically. There are two methods to carry out the reset discharge in all the cells. One method is that, as shown in FIG. 4(A), a discharge of certain level is carried out when the first subfield at the top of a frame (or a field) is initiated, and in this case, the all the cells reset discharge is not carried out in the second subfield and latter ones. This has been disclosed in Japanese Patent No. 2756053. The other method is that, as shown in FIG. 4(B), a discharge of a small level is carried out in the reset period of all the cells. By using these methods, a display contrast of a ratio about 300:1 to 600:1 can be attained in a dark room. Concretely, the brightness is 1 cd/m2 or less. Moreover, there may be another method, a combination of the two methods, that is, a reset with no or little light emission is carried out once in a frame or a field.
FIG. 5 is a diagram that illustrates the drive waveforms of the apparatus in FIG. 1, which is the example disclosed in Japanese Patent No. 2772753. In the reset period, a pulse of a high voltage, for example 300 V, greater than the discharge start voltage, is applied to the X electrode. By applying a pulse, a discharge is caused to occur in all the cells, regardless of the lighting state in the preceding subfield, and the wall charges are formed. When the pulse is removed, a discharge is caused to occur again by the voltage due to the wall charges themselves, but the space charges generated by the discharge are neutralized and a uniform state in which no wall charge exists can be established, because there is no voltage difference between electrodes. Although almost all charges are neutralized, a certain amount of ions and metastable atoms remains in the discharge space and works as a priming fire to cause the address discharge to occur without fail. This is called, in general, the pilot effect or the priming effect. In the address period, a scanning pulse is applied to the Y electrode, which is an electrode for scanning, and an address pulse is applied to the address electrode of the cell to be made to emit light and a discharge is caused to occur. This discharge propagates to the X electrode side and wall charges are formed between the X electrode and the Y electrode. This scanning is carried out on all the display lines. Then, in the sustain discharge period, a sustain pulse of Vs voltage (about 170 V) is applied repeatedly. The cell on which wall charges are formed by the address discharge initiates a discharge, because the voltage of the wall charges are added to the sustain pulse voltage and the total voltage becomes more than the discharge start voltage. The cell in which no address discharge is caused to occur does not initiate a discharge because there is no wall charge on the cell.
FIG. 6 is a drive waveform chart in the subfield where no reset discharge of all cells is carried out, and each corresponds to SF2 to SF10, respectively, in FIG. 4(A). In the reset period, an erasing pulse of Vs voltage with a gradual slope is applied and a discharge is caused to occur only in the cell that emitted light, in the preceding subfield, to eliminate the wall charges. The actions in the address period and the sustain period are the same as those in FIG. 5. Therefore, the discharge that occurs in the reset period in this method is one that relates to the display data of the preceding subfield and the contrast is not degraded.
FIG. 7 is a diagram that shows the rough structure of the plasma display of another method disclosed in EP 0 762 373 A2. This method is called the ALIS (Alternate Lighting of Surfaces) method, in which the X electrodes and the Y electrodes, which are display electrodes, are spaced equally by turns and every slit between electrodes are used as a display line. Because every slit between electrodes is used as a display line, the number of electrodes is about half that in FIG. 2, therefore, this method has advantages in that the cost is reduced and the definition is improved.
FIG. 8 is a diagram that shows the principles of light emission. Because every slit between all the electrodes is a display line, it is impossible to light all the display lines at the same time. Therefore, an interlaced display, in which the lighting periods for the odd-numbered lines and the even-numbered lines are separated, is employed.
FIG. 9 is a diagram that shows the structure of a frame of the ALIS method, and a frame is divided into two fields and each field comprises plural subfields. In the first field the odd-numbered lines are used for display and in the second field, the even-numbered lines are used for display.
FIG. 10 is a diagram that shows the drive waveforms of the plasma display panel of the ALIS method disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2000-75835. The reset period comprises a write period during which a weak write discharge is caused to occur by the first pulse with a gradual slope, and an erase period during which an erasing discharge is caused to occur by the latter pulse. Because these discharges are weak, the amount of emitted light is suppressed to a low level. Therefore, even if this reset discharge is carried out in all the cells of all the subfields, the brightness of black level is never raised. This corresponds to the situation in FIG. 4(B).
As described above, the brightness of black display of the plasma display panel is suppressed to a low level by improving the drive waveforms and the sequence, and the contrast ratio in a dark room is accomplished to 300:1 to 600:1. Also white brightness 600 cd/m2 is accomplished in a small area, but an optical filter whose light transparency is 50 to 60% is provided in the display apparatus that is used actually, to prevent the contrast in a light room from deteriorating because of the deflection of outside light on the panel surface. Although the panel itself has a brightness of 600 cd/m2, that after the passing through the filter becomes to 300 cd/m2 or so. For a CRT type TV sold commercially, the peak brightness is about 500 cd/m2, and a higher brightness is required for the plasma display. To meet these demands, fluorescent materials for a higher brightness have been developed and applied, but this results in an increase in the brightness of the black level. In the case where the dark room contrast is 500:1 and the peak brightness is 500 cd/M2 with a filter attached, the brightness of black level becomes 1 cd/M2. When a movie is viewed in a situation close to a dark room, 1 cd/m2 is too bright and the degradation of the display cannot be ignored.
Moreover, there is an example in which a dark room contrast of about 3000:1 is achieved on the panel that has the cell structure as shown in FIG. 2 by carrying out the reset method only once to the frame or field as shown in (A) after applying the reset method in which weak light is emitted as shown in FIG. 4(B). But it is restricted to the panel that has a cell structure in which the distance between neighboring cells are large as shown in FIG. 2, therefore, such method cannot be simply realized on the ALIS method panel. The reason is described below with reference to FIGS. 11A through 11D and FIGS. 12A through 12D.
FIGS. 11A through 11D are diagrams that show the examples of the discharge conditions when the plasma display panel of ALICE method is operated with the drive waveforms in FIG. 10 and a large voltage as shown in FIG. 4 (A) is applied between the X electrode and the Y electrode. FIG. 11A is a diagram that shows the case where a sustain discharge is carried out in a cell formed by X2 and Y2 in the immediately preceding subfield. In this case, the electrons generated by the sustain discharge diffuse as far as X3 and Y1, which are neighboring electrodes, and are accumulated as wall charges. In the case of the conventional plasma display panel shown in FIG. 2, such accumulation of electrons on the neighboring electrodes does not occur because the distance between the Y1 electrode and the X2 electrode, and that between the Y2 electrode and the X3 electrode are great. Then, in the reset period, an erasing pulse of negative 100 V with a gradual slope is applied to the X electrode, and the wall charges are decreased by the erasing discharge between X2 and Y2 with t1 timing as shown in FIG. 11B. Then a write pulse of voltage Vs (170 V) is applied to the Y electrode and a discharge is caused to occur again as shown in FIG. 11C. The voltage between the X electrode and the Y electrode at this time is 270 V and exceeds the discharge start voltage (about 220 V), therefore, wall charges are formed. Wall charges are formed in all the cells and, subsequently, with the voltage of the X electrode being fixed to 70 V (Vx), an erasing pulse with a gradual slope that reaches as low as negative 150 V is applied to the Y electrode. This pulse causes a discharge to occur again, but because the final voltage of the erasing pulse is the same as the discharge start voltage, almost all the wall charges are neutralized at the end and a state in which almost no wall charges exist can be realized in all the cells, as shown in FIG. 11D.
Next, the reset period in which reset is carried out in the second and latter subfields is considered. FIGS. 12A through 12D are diagrams that show examples of discharge action in this case, and the voltage applied to the X electrode is changed from negative 100V to 0 V with the timing shown in FIG. 12C to carry out discharge only in cells lit in the preceding subfield to perform erasing. In this case, if the wall charges on X2 and Y2 have the polarity that increases the voltage between electrodes, the cell discharge occurs between X2 and Y2 and wall charges are eliminated. The negative charges remaining on X3 also increase the voltage between electrodes, therefore, an erasing discharge is caused to occur between the X3 and Y3 electrodes and charges are neutralized. The negative charges remaining on the Y1 electrode, however, remain because the negative charges have a polarity that cancels the applied voltage and no discharge is caused to occur. Therefore, after the reset period is completed, negative charges remain on the Y electrode. If such residual wall charges exist, a scanning pulse is applied in the address period and a discharge may be caused to occur even if no address pulse is applied, resulting in an unstable performance.
In addition, in the case in which such reset action as shown in FIG. 4(B) is carried out, it is possible to suppress the intensity of light emission caused by the reset discharge by decreasing the negative voltage applied to the X electrode with the timing t2 in FIG. 10. FIG. 13 is a diagram that shows the relation between the voltage of reset discharge and the brightness attained by the reset discharge. As shown in FIG. 13, for example, it is possible to lower the brightness by decreasing the voltage between the X and Y electrodes to be applied with the timing t2 in FIG. 10. It is found, however, that the reset action becomes insufficient for the stable display when the voltage drops below 260 V. An example case is where the voltage to be applied to the Y electrode is Vs =170 V, and the negative voltage to be applied to the X electrode is 90 V or lower. In this case also, the negative charges that remain on the Y electrode cancel the applied voltage, therefore, the reset discharge cannot be carried out sufficiently.
Taking these phenomena into consideration, if the negative voltage to be applied to the X electrode is set to around 100 V and the brightness is set to 1.2 cd/m2, a contrast of 500:1 is attained.
In addition, a method, in which narrow reset pulses are used in the PDP of the ALIS type and the reset discharge is carried out in a lit cell and the cell contiguous thereto, has been disclosed in Unexamined Patent Publication (Kokai) No. 11-338414. In this method, the reset discharge is carried out only in the lit cell and the adjacent cell, therefore, there is no light emission for black display and the dark room contrast is excellent. However, whether or not the reset discharge can be carried out in the cell contiguous to the lit cell depends on the pulse width and voltage, therefore, it used to be very difficult to cause a discharge to occur stably in all the cells that have variations in characteristics such as the discharge start voltage.
As explained above, the problem is that a sufficient contrast cannot be attained under the conditions in which stable actions are ensured in the PDP of the ALIS type.
In the case of a CRT, a situation in which 0 cd/M2 is almost reached has been realized, and the same accomplishment in a plasma display panel is eagerly expected, as well as in the case of a PDP of ALIS type.
The object of the present invention is to realize a method of driving a plasma display panel of the ALIS type, in which the brightness of light emission for black display is lowered, performance is stable, and the contrast is very high.
In order to attain the above-mentioned object, the method of driving a plasma display panel of the ALIS type of the present invention is characterized in that even when a voltage, which changes gradually as time goes by, is applied between the first and the second electrodes to cause a discharge to occur only in the cell lit in the preceding subfield, a neighboring cell write period, during which the residual wall discharges on one side of the electrode of the different display line contiguous to the cell lit in the preceding subfield are eliminated, is provided before or after the write period.
According to the present invention, when the conventional drive method is carried out, the wall discharges remaining on one of the electrode of a different display line, contiguous to the cell that was lit in the preceding subfield, are eliminated. The wall charges remaining on the other electrode of the display line are eliminated at the same time when the wall charges in the cell that was lit in the preceding subfield are eliminated, as is conventional. Therefore, the present invention realizes a state in which almost no wall charge exists on all the cells. Moreover, the discharge caused by elimination is very weak and the degradation of the contrast is small.
The neighboring cell write action is carried out to eliminate the wall charges, which leaked and were accumulated by being contiguous to the cell that was lit and were not eliminated by a small applied voltage, because the polarity of the applied voltage is reverse and no reset discharge is caused to occur in the write period. The wall charges generated in the neighboring cell write period do not affect the write period, therefore, it can be carried out before or after the write period.
As shown in FIG. 4(A), when a frame (or a field) is composed of plural subfields and charged particles and metastable atoms are generated to keep the conditions under which discharge is easily caused to occur (priming effect or pilot effect), by applying a large voltage only to the top subfield of a frame to carry out the reset discharge with a strong intensity of light emission on all the cells, the present invention is applied to the reset period of other subfields. Particularly in the case of the ALIS method, the interlaced drive as shown in FIG. 9 is carried out, and it is acceptable in this case that the reset discharge in all the cells is carried out in the top subfield of the first frame, that is, the first field, and the present invention is applied to the reset periods in other subfields, or that the reset discharge in all the cells is carried out in the top subfields in the first and the second fields, and the present invention is applied to the reset periods of other subfields. When the reset discharge in all the cells is carried out in the top subfields of the first and the second fields, the subsequent actions can be carried out stably because the part that is not used in the preceding field is activated. In the case in which the reset discharge in all the cells is carried out only in the top subfield of the first field, the brightness during black display is nearly halved.
It is advisable to further provide an erase period, in which an address prepare voltage waveform with a gradual slope is applied so that the voltage between the first and the second electrodes becomes greater than the discharge start voltage, after both the write period and the neighboring cell write period are carried out.
Moreover, in the PDP with surface discharge of three electrodes, the discharge start voltage between the address electrode and the Y electrode is lower in general compared to that between the X electrode and the Y electrode, but a discharge toward the third electrode with a voltage exceeding the discharge start voltage never occurs because the voltage applied to the third electrode is selected between the maximum and the minimum voltages applied to the first and the second electrodes.